The present invention relates to the field of electrical circuitry, and more particularly relates to the fabrication of individual panels with multiple layers.
There continues to be an ever increasing need for multi-layer electronic assemblies which provide high density, complex interconnections for electrical components. Methods for forming multi-layer electronic assemblies are taught in Dux et al., U.S. Pat. No. 5,224,265 and Ehrenberg et al. U.S. Pat. No. 5,232,548. The '265 patent discloses a high-density, multi-layer thin film structure and process for making a multi-layer structure wherein multiple individually testable sub-units are fabricated in parallel, pre-tested for operational performance, and joined together to form a three dimensional wiring matrix.
Commonly assigned U.S. Pat. No. 5,590,460 to DiStefano et al., the disclosure of which is incorporated by reference herein, teaches a process for making a multi-layered assembly including providing a sheet of a dielectric material having a top and a bottom surface. Layers of a temporary layer susceptible to etching are coated on the top and bottom surfaces of the dielectric sheet, respectively. Photoresist layers are then applied over the top and bottom temporary layers and are photographically exposed to develop openings which are perpendicular to the external surfaces of the assembly. The assembly is then exposed to an etchant to form aligned apertures in the top and bottom temporary layers. After formation of the holes, an electrically conductive structural material such as a metal is deposited within each hole and within the apertures in the top and bottom temporary layers. A structural material is then applied as a continuous layer covering the peripheral surfaces of the holes in the sheet and also covering the peripheral walls of the apertures in the temporary layers.
Despite these and other efforts in the art, there are needs for still further improvement.